ddu37f mechanically variable ttl delay line (series ddu37f) features packages ? ideal for ?set and forget? applications ? multi-turn adjustment screw (approx. 40 turns) ? input & output fully ttl interfaced & buffered (10 t 2 l fan-out capability) ? resolution: as low as 0.12ns ? minimum delay ( t d0 ): 6ns typical ? output rise time: 2ns typical ? min. input pulse w i dth: 20% of maximum delay ? pow e r dissipation: 230mw maximum ? operating temperature: 0 to 70 c (commercial) -55 to 125 c (military) ? temperature coefficient: 100 ppm/ c functional description the ddu37f-series device is a mechanica lly variable, fast-ttl interfaced delay line. the signal input (in) is reproduced at the tap output (out), shifted by an amount which can be adjusted between t d0 and t d0 + t dvar , where t dvar is given by the device dash number (see table). the device operates from a single 5v supply and is ttl interfaced, capable of driving up to 10 ttl loads. series specifications func t i ona l d i a g r a m gn d in ou t .565 ma x 1. 750 .285 .020 p a ck ag e di me n s i o n s .187 .125 .200 mi n .430 .100 in gn d nc ou t vc c 1.640 .100 .200 .100 .060 .060 d a ta delay devices, i n c. ? 3 ddu37f gn d in out n c vc c ddu37 f - x x ( com m er ci a l ) ddu37 f - x x m ( m ilit a r y ) xx = d a s h n u m b e r pin descriptions in signal input out fixed output vcc +5v gnd ground nc no connection dash number specifications part number t dva r (ns) d d u 3 7 f - 2 5 1 5 d d u 3 7 f - 3 0 2 0 d d u 3 7 f - 4 0 3 0 d d u 3 7 f - 5 0 4 0 d d u 3 7 f - 6 0 5 0 d d u 3 7 f - 7 0 6 0 d d u 3 7 f - 8 0 7 0 d d u 3 7 f - 1 0 0 9 0 d d u 3 7 f - 1 2 0 1 0 0 d d u 3 7 f - 1 5 0 1 3 0 d d u 3 7 f - 2 0 0 1 7 0 note: other delay times av ailable on request ? 2008 data dela y dev i ces doc #01016 data delay devices, inc. 1 1/11/2008 3 mt. prospect ave. clifton, nj 07013
ddu37f application notes high frequency response the ddu37f tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. although the device will function properly for pulse widths as small as 20% of the total delay and periods as small as 40% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. however, for a given input condition, the deviation will be repeatable from pulse to pulse. contact technical support at data delay devices if your application requires device testing at a specific input condition. power supply bypassing the ddu37f relies on a stable power supply to produce repeatable delays within the stated tolerances. a 0.1uf capac itor from vcc to gnd, located as close as possible to the vcc pin, is recommended. a wide vcc trace and a clean ground plane should be used. device specifications table 1: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v cc - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 2: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s high level output voltage v oh 2 . 5 3 . 4 v v cc = mi n, i oh = max v ih = mi n, v il = max low level output voltage v ol 0 . 3 5 0 . 5 v v cc = mi n, i ol = max v ih = mi n, v il = max high level output current i oh - 1 . 0 m a low level output current i ol 2 0 . 0 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v input clamp voltage v ik - 1 . 2 v v cc = mi n, i i = i ik input current at maximum input voltage i ihh 0 . 1 m a v cc = max, v i = 7.0v high level input current i ih 2 0 a v cc = max, v i = 2.7v low level input current i il - 0 . 6 m a v cc = max, v i = 0.5v short-circuit output current i os - 6 0 - 1 5 0 m a v cc = max output high fan-out 25 unit output low fan-out 12.5 load doc #01016 data delay devices, inc. 2 1/11/2008 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
ddu37f delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 1 fast-ttl gate supply voltage (vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.5 x total delay period: per in = 10 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. in out out tr ig in tr ig t est set u p de v i ce unde r test ( d u t ) os ci llos c op e pu l s e ge ne ra tor t i ming dia g r a m for t e s t ing d rise d fall per in pw in t rise t fall 0. 6 0. 6 1. 5 1. 5 2. 4 2 . 4 1. 5 1. 5 v ih v il v oh v ol input sig n al out p ut sig n al doc #01016 data delay devices, inc. 3 1/11/2008 3 mt. prospect ave. clifton, nj 07013
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